Friday, 6 September 2013

Free download study note on What is polled and interrupt modes of data transfer for amie section B

Main characteristic of interrupt modes of data transfer is that data exchange between peripheral and the processor is initiated by the device. The interrupt modes of data transfer are the same like normal Interrupt process in microprocessor 8085.

 This mode is basically used for data transfer between slow peripherals and processor, and also when the occurrence of data is unpredictable in nature.
 In billow I discuss on the details steps of interrupt modes of data transfer
 An interrupt is requested by a peripheral device to processor.
 After getting interrupt request an acknowledgement of the request is send by the processor at the end of the execution of the current instruction.
 The program then moves to Interrupt Service Subroutine (ISS) program at which the program corresponding to the interrupting device is already stored. The return address is stored in the stack pointer along with other register contents as per program needs.
 Data transfer takes place under ISS.
 Interrupt system is enabled.
 The program then returns to the main program after loading the return address from stack in program counter (PC).
See the flowchart corresponding to this scheme to understand better way.

Polled interrupt system.
Polled interrupt can be of two types those are a) Software polled interrupt scheme b) Hardware polled interrupt scheme .Polled interrupt is used when many devices are connected to the system. In a polled interrupt scheme, each device is tested, using either hardware or software, until the device which has requested the interrupt, is identified. Corresponding to the device thus identified, the program is then diverted to the ISS written for that device.

Hardware polling scheme.
Let we take an example first to understand Hardware polling scheme. In hardware polling scheme involving four devices is shown below. This scheme is also known as ‘daisy-chaining’. The four device status flags from the four devices are ORed and taken to the INTR pin of the processor. A low INTA is issued by the processor at the end of the current instruction execution. The INTA signal is passed on to device 1—the highest priority device. If device 1 has interrupted the processor then it will identify itself with the data bus. If not, the INTA signal is passed on to device 2 and so on. Thus it is apparent that device 4 has got the lowest priority.

Software polling scheme
As like hardware polling we also take an example to understand the software polling scheme .The flowchart for software polling scheme is shown below. It shows four devices whose status is to be checked in software one after the other. As per the scheme, device 1 has the highest priority while the lowest priority device is device 4. The status of each device is ORed and connected to INTR pin of the processor. On occurrence of an interrupt, the flag of each device is tested as per the software polling scheme.

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